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QHx220
Power ON/OFF Sequence
Power ON
Slope1: >1.8V/50ms
VDDA & VDDA2
0V
Power ON
1.8V
t1>0
ENBAR
BUS ENABLE
Low
Low
t2>250μs
CLK
DATA
Low
Low
1
MSB
23
22
2
21
3
20
4
19
5
18
6
17
7
16
8
15
9
10
14
11
13
12
12
13
11
14
10
9
15
8
16
7
17
6
18
5
19
4
20
3
21
2
22
1
23
24
LSB
0
I-DAC
Q-DAC
Freq. Range Gain
Spare
(10 bits: 0111111111)
(10 bits: 0111111111)
(MTV: 00)
(0)
(0)
(This command sets QHx220 into minimum gain (Note 8))
Power OFF
Power OFF
VDDA & VDDA2
1.8V
Slope2: >1.8V/50ms
0V
ENBAR
Low
BUS ENABLE
Low
CLK
Low
DATA
Low
NOTES:
8. When the chip is powered up its register are all zero. This means -135° phase and full analog gain, WLAN Application and 0dB
coarse gain (the boost gain mode is not enabled).
9. VDDA and VDDA2 should be connected on the PCB and decoupled with caps right next to the pin.
10. The SPI Bus is not accessible when VDDA/VDDA2 are <1V.
6
FN6986.0
October 20, 2009
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